The present invention is generally related to the field of Electronic Design Automation (EDA) and more particularly to deterministic and statistical static timing convergence of Very Large Scale Integrated (VLSI) designs.
Synchronous digital systems consist of a network of computation nodes (combinational logic gates) and memory elements (registers). Each register is controlled by a clock signal and depending on the state of the clock, the data at the register input is either effectively isolated from its output or transmitted to the output.
The measure of digital circuit performance of synchronous digital systems has traditionally been the operational clock frequency of the design. Static timing analysis (STA) techniques are commonly used to ensure that the digital circuit design meets the clock frequency targets. Static timing analysis methods compare the target frequency of the design with the frequency of operation of the circuit and identify the circuit which would need to be optimized to meet the frequency goals.
Static timing analysis computer aided design tools (CAD) computes the latest and earliest arrival times of signals within a digital circuit. In order to compute the arrival times of the signals static timing analysis does delay measurements across the circuit elements (typically gates) using pre-characterized library data.
In a synchronous system, in order for a register to operate correctly when the clock signal arrives, a timing analysis program is primarily concerned with two kinds of timing errors. A setup fail occurs when the data signal arrives too late and misses the clock signal. A hold fail occurs when the data signal changes too early after the clock transition. The arrival time of a signal can vary because of numerous factors such as the logical implementation of the circuit, operating conditions and the manufacturing variability. Although these delay measurements can be done through circuit simulations such an approach is likely to be exponentially runtime prohibitive to be of any practical significance for even small designs.
Another benefit of STA is that it is a vector-less or vector independent approach of measuring circuit performance. STA techniques are algorithmically fast, efficient and provide an accurate analysis of circuit performance in synchronous digital systems. The objective of STA to provide complete coverage of the entire design and analyze every path as opposed to vector based circuit simulations.
The impact of process variability in modern day chip designs and manufacturing is significant in terms of the timing performance of a given VLSI circuit. In addition to process variability, environmental variations (e.g., variations in power supply VDD and temperature) contribute to the uncertainty in the design timing characteristics. Statistical Static Timing Analysis (SSTA) has subsequently emerged as a solution to address the issues and considers the impact of variations during timing analysis and optimization. In SSTA, timing quantities, such as delays and slews are treated as random variables with known distributions. Each timing quantity may be sensitive to multiple global sources of variability which are termed parameters. Moreover, a timing quantity is also considered to be sensitive to an uncorrelated or local source of variability.
The design, development, and manufacturing of very large scale integrated circuits (VLSI) is a complex effort. The chip designs are increasing both in size and complexity with each technology generation. In order to design such massive System on Chips (SoCs) and multi-core microprocessors, hierarchical design techniques are commonly used.
Hierarchical design techniques involve dividing a design represented by a chip-level netlist into more manageable components. These components are known as hierarchical components or design components. These can be sub-divided further into additional hierarchical components.
Hierarchical design techniques offer several advantages. Geographically, dispersed engineering teams can concurrently work on the design and development activities of these hierarchical components. This enables the design activities to be managed more efficiently. From an Electronic Design Automation (EDA) perspective, this brings higher tool capacities, practical tool runtimes and memory requirements. Another advantage is the ability to share and reuse design components across multiple designs and design teams.
Despite the above advantages, hierarchical design techniques rely on the use of abstract models for compact representation. A wide variety of abstract models are available for hierarchical deterministic or statistical static timing analysis. These models typically tradeoff accuracy for compact representation and add to the analysis complexity.
Existing techniques involve recursive hierarchical static timing analysis on the lower level component and the upper level component. The results from the static timing analysis of the upper level component are feedback for updating the constraints for the lower level block and the results of the static timing analysis of the lower level block are feedback for updating the abstract representation at the upper level block. This basic approach although primitive provided faster STA runtimes as compared to conventional flat STA runtimes.
However, this approach is not ideal, since design reuse and concurrent design is disabled. Additionally, the approach is extremely recursive or iterative which increases timing convergence TAT. Typically, designers working on a complex processor design or a SOC perform numerous (e.g., more than 25 design iterations) before they can converge. Each of these design iterations can trigger recursive timing iterations which can significantly increase the design TAT.
As designs become larger and more complex, hierarchical design techniques are essential. Concurrency and design reuse have to be an integral part of the hierarchical design methodology. However, design construction/closure iterations should be minimized and timing pessimism should be reduced to enable accurate and efficient timing analysis.